fpga_load does not work when passing the chameleon memory address as argument if it is compiled with 64bits

During the improvements of scan_system in BoxPcs (BL51) to dynamically load the chamaleon table instead of using a hardcoded set of IP Cores (described within a template), we detected that the fpga_load does not work if the binary is compiled in the target (64 bits) but it works if using the precompiled fpga_load (32 bits).

Below, the error:

men@men-BL51:/opt/menlinux/TOOLS/FPGA_LOAD$ sudo ./fpga_load -k 0xf000e000 -t -v
[sudo] password for men: 
Z100_IsaInit
*** ERROR: no chameleon table found at address 0x32f000e000 (0xc2)
*** ERROR: can't find device 0x02d
*** ERROR: Chameleon table or flash interface not found (0x2018)

However, if we put the run the stock binary:

men@men-BL51:~/rodriguez/13MD05-90/MDISforLinux/BIN$ sudo ./fpga_load -k 0xf000e000 -t -v
Z100_IsaInit

Chameleon FPGA table for device 0xf000e000:
  BAR0: 0x00000000; size: 0x00001000, mapType: IO;
  BAR1: 0xf0000000; size: 0x00010000, mapType: MEM;
  BAR2: 0x00000000; size: 0x00000000, mapType: unused;
  BAR3: 0x00000000; size: 0x00000000, mapType: unused;
  BAR4: 0x00000000; size: 0x00000000, mapType: unused;
  BAR5: 0x00000000; size: 0x00000000, mapType: unused;

Information about the Chameleon FPGA:
FPGA File=' 16SC31-00A0' table model=0x41('A') Revision 0.0 Magic 0xABCE
List of the Chameleon units:
Idx DevId  Module                   Grp Inst Var Rev IRQ BAR Offset     Address
--- ------ ------------------------ --- ---- --- --- --- --- ---------- ----------
  0 0x007d 16Z125_UART                0    4   0  17   6   0 0x00000220 0x220
  1 0x007d 16Z125_UART                0    0   0  17   4   0 0x000003f8 0x3f8
  2 0x007d 16Z125_UART                0    1   0  17   3   0 0x000002f8 0x2f8
  3 0x007d 16Z125_UART                0    2   0  17   7   0 0x000003e8 0x3e8
  4 0x007d 16Z125_UART                0    3   0  17   5   0 0x000002e8 0x2e8
  5 0x0052 16Z082_IMPULSE             0    0   0   2  63   1 0x00000800 0xf0000800
  6 0x0022 16Z034_GPIO                0    0   0  10  11   1 0x0000e200 0xf000e200
  7 0x0022 16Z034_GPIO                0    2   0  10  11   1 0x0000e240 0xf000e240
  8 0x0025 16Z037_GPIO                0    0   1   1  11   1 0x0000e260 0xf000e260
  9 0x007e 16Z126_SERFLASH            0    0   1   6  63   1 0x0000e280 0xf000e280
 10 0x001d 16Z029_CAN                 0    0   0  18  11   1 0x0000e400 0xf000e400
 11 0x004c 16Z076_QSPI                0    0   0   7  11   1 0x0000e800 0xf000e800
 12 0x001d 16Z029_CAN                 0    1   0  18  11   1 0x0000f000 0xf000f000

 Current FPGA file/usage status: ** invalid, Check FPGA programming.